A FLOTOX (Floating Gate Tunnel Oxide) type EEPROM (Electrically Erasable and Programmable ROM) is a semiconductor memory including a nonvolatile memory cell constituted by a stacked-gate type memory cell transistor and a select transistor connected in series to the cell transistor. Such type of EEPROM has a tunnel window which is formed in a portion serving as an electron passage during write/erase operation of data in a gate insulating film formed on a semiconductor substrate, and is thinner than a peripheral gate insulating film. A floating gate is formed on the tunnel window and a select gate is formed at a portion spaced from the tunnel window in the gate insulating film.
In the semiconductor device of related art, a plurality of element forming regions is formed on a front surface of a base substrate (wafer) made of silicon and a gate oxide film is formed by oxidizing each of the element forming regions. Subsequently, a tunnel oxide film having a reduced thickness is formed by partially etching the gate oxide film in a predetermined element forming region. In addition, a channel is formed by injecting ions into the base substrate and first and second memory cell diffusion layers of n− type are formed. Subsequently, a polysilicon layer is formed on the gate oxide film. Then, the polysilicon layer is masked by a resist pattern and is etched into a predetermined pattern of polysilicon layer. Thus, a floating gate and a select gate constituted by the remaining polysilicon layer are simultaneously formed on the gate oxide film. Thereafter, an insulating ONO (Oxide-Nitride-Oxide) film is formed on front and side surfaces of the floating gate and a control gate is further formed on the ONO film to cover the front and side surfaces of the floating gate.
However, in the semiconductor device of the related art, since the control gate covers both of the front and side surfaces of the floating gate, there is a need of an extra space on the semiconductor substrate by a thickness of the control gate covering the side surfaces, which has a limit on cell miniaturization. If the side surfaces of the control gate are coplanar with the side surfaces of the floating gate, the miniaturization problem may be overcome. However, no matter how high the alignment accuracy, it is very difficult to form the control gate having the same shape as the patterned floating gate. Therefore, there is a problem of a positional deviation between the floating gate and the control gate which causes a variation in a threshold voltage.